17946147. DOUBLE-SIDED EMBEDDED MEMORY ARRAY simplified abstract (International Business Machines Corporation)

DOUBLE-SIDED EMBEDDED MEMORY ARRAY

Organization Name

International Business Machines Corporation

Inventor(s)

Wu-Chang Tsai of Albany NY (US)

Ailian Zhao of Slingerlands NY (US)

Ashim Dutta of Clifton Park NY (US)

Chih-Chao Yang of Glenmont NY (US)

DOUBLE-SIDED EMBEDDED MEMORY ARRAY - A simplified explanation of the abstract

This abstract first appeared for US patent application 17946147 titled 'DOUBLE-SIDED EMBEDDED MEMORY ARRAY

Simplified Explanation

A semiconductor structure is presented that integrates two different types of memory devices into a single CMOS chip by directly connecting a first memory array and a second memory array using nanosheet stacks and backside contacts. The structure defines a double-sided memory array on a CMOS wafer.

• The first memory array and second memory array are directly connected by nanosheet stacks and backside contacts.
• The nanosheet stacks separate the first memory array from the second memory array.
• The structure integrates two different types of memory devices into a single CMOS chip.

Potential Applications

This semiconductor structure could be used in:

• High-performance computing
• Data storage applications
• Mobile devices

Problems Solved

This technology solves the following problems:

• Integration of different memory devices on a single chip
• Improving memory array density
• Enhancing overall performance of memory systems

Benefits

The benefits of this technology include:

• Increased memory capacity
• Improved data transfer speeds
• Enhanced overall efficiency of memory systems

Potential Commercial Applications

Potential commercial applications of this technology include:

• Memory chips for consumer electronics
• Data centers
• Cloud computing servers

Possible Prior Art

One possible prior art for this technology could be the integration of different memory devices on a single chip using traditional interconnect technologies.

How does this technology impact power consumption in memory systems?

This article does not provide information on the potential impact of this technology on power consumption in memory systems. Further research is needed to understand the power efficiency of this semiconductor structure.

What are the potential challenges in manufacturing this semiconductor structure at scale?

The article does not address the potential challenges in manufacturing this semiconductor structure at scale. It would be important to investigate the scalability and production feasibility of this technology for mass production.

Original Abstract Submitted

A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.