17942822. Pillar Based Memory (MRAM) Embedded within the Buried Power Rail within a Backside Power Distribution Network simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

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Pillar Based Memory (MRAM) Embedded within the Buried Power Rail within a Backside Power Distribution Network

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Wu-Chang Tsai of Albany NY (US)

Alexander Reznicek of Troy NY (US)

Michael Rizzolo of Delmar NY (US)

Ailian Zhao of Slingerlands NY (US)

Pillar Based Memory (MRAM) Embedded within the Buried Power Rail within a Backside Power Distribution Network - A simplified explanation of the abstract

This abstract first appeared for US patent application 17942822 titled 'Pillar Based Memory (MRAM) Embedded within the Buried Power Rail within a Backside Power Distribution Network

Simplified Explanation

The patent application describes an apparatus with a backside power distribution network, a backside power rail connected to the network, and a backside contact via linking at least one front end of line transistor to the backside power rail, with the backside contact via featuring a pillar-based memory device.

  • Backside power distribution network
  • Backside power rail
  • Backside contact via with a pillar-based memory device

Potential Applications

This technology could be applied in the semiconductor industry for improving power distribution and connectivity in electronic devices.

Problems Solved

1. Enhanced power distribution efficiency 2. Improved connectivity for front end of line transistors

Benefits

1. Increased performance of electronic devices 2. Enhanced reliability of power distribution 3. Simplified manufacturing processes

Potential Commercial Applications

Optimizing Power Distribution in Semiconductor Devices


Original Abstract Submitted

An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via that couples at least one front end of line transistor to the backside power rail; wherein the backside contact via comprises a pillar based memory device.