17941092. SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING A FLOATING STATE OF ADJACENT WORD LINES AND AN OPERATING METHOD THEREOF simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING A FLOATING STATE OF ADJACENT WORD LINES AND AN OPERATING METHOD THEREOF

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Hyunkook Park of Suwon-si (KR)

Sara Choi of Suwon-si (KR)

SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING A FLOATING STATE OF ADJACENT WORD LINES AND AN OPERATING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17941092 titled 'SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING A FLOATING STATE OF ADJACENT WORD LINES AND AN OPERATING METHOD THEREOF

Simplified Explanation

The abstract describes a semiconductor memory device that includes two memory cells for storing multi-bit data. The device has two word lines, one connected to the first memory cell and the other adjacent to it and connected to the second memory cell.

• The device applies different voltage levels to the word lines during the reading process.
• The first period applies a high voltage level to read the first bit of data from the multi-bit data stored in the first memory cell.
• The second period applies a lower voltage level to the word lines, and during this period, the second word line is in a floating state.
• The third period applies a higher voltage level to read the second bit of data from the multi-bit data stored in the first memory cell.

Potential applications of this technology:

• Memory devices in electronic devices such as smartphones, tablets, and computers.
• Data storage in servers and data centers.
• Embedded memory in various electronic systems.

Problems solved by this technology:

• Efficient reading of multi-bit data stored in memory cells.
• Minimizing power consumption during the reading process.
• Reducing interference between adjacent word lines.

Benefits of this technology:

• Improved performance and speed in reading multi-bit data.
• Lower power consumption and energy efficiency.
• Enhanced reliability and accuracy in data retrieval.

Original Abstract Submitted

A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.