17939327. MEMORY DEVICE INCLUDING ROW HAMMER PREVENTING CIRCUITRY AND AN OPERATING METHOD OF THE MEMORY DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
MEMORY DEVICE INCLUDING ROW HAMMER PREVENTING CIRCUITRY AND AN OPERATING METHOD OF THE MEMORY DEVICE
Organization Name
Inventor(s)
Jungmin You of Hwaseong-si (KR)
MEMORY DEVICE INCLUDING ROW HAMMER PREVENTING CIRCUITRY AND AN OPERATING METHOD OF THE MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17939327 titled 'MEMORY DEVICE INCLUDING ROW HAMMER PREVENTING CIRCUITRY AND AN OPERATING METHOD OF THE MEMORY DEVICE
Simplified Explanation
The abstract describes a row hammer preventing circuitry that aims to prevent a specific type of computer memory vulnerability known as "row hammering". This vulnerability occurs when repeated accesses to certain rows of memory cause bit flips in adjacent rows, potentially leading to security breaches or system crashes.
- The circuitry includes a first table that stores a count value and an address bit for each entry, representing the number of times a specific row has been accessed.
- A second table includes safe bits and a safe bit counter, which keep track of the number of safe bits in each entry.
- The row hammer preventing logic identifies entries on which a masking comparison needs to be performed based on the safe bit counter.
- The logic determines whether there is a match between the address bits of the access-requested target row and the masking entries, excluding the most significant bit (MSB).
- If a match is found, indicating a potential row hammering vulnerability, a control signal is generated to trigger an additional refresh on rows adjacent to the vulnerable row.
Potential applications of this technology:
- Computer memory systems: The row hammer preventing circuitry can be implemented in various computer memory systems, such as DRAM (Dynamic Random-Access Memory), to mitigate the risk of row hammering vulnerabilities.
- Data centers: Large-scale data centers that heavily rely on memory-intensive applications can benefit from this technology to enhance the security and reliability of their systems.
Problems solved by this technology:
- Row hammering vulnerability: The circuitry addresses the issue of row hammering, a specific type of memory vulnerability that can lead to security breaches or system crashes.
- Bit flips in adjacent rows: By identifying and refreshing rows adjacent to vulnerable rows, the circuitry prevents bit flips caused by repeated accesses, reducing the risk of data corruption or unauthorized access.
Benefits of this technology:
- Enhanced security: By preventing row hammering vulnerabilities, the circuitry helps protect sensitive data from potential attacks or unauthorized access.
- Improved system reliability: By mitigating the risk of bit flips in adjacent rows, the circuitry contributes to the overall stability and reliability of computer memory systems.
- Cost-effective solution: The circuitry can be implemented in existing memory systems without requiring significant hardware modifications, making it a cost-effective solution for enhancing memory security.
Original Abstract Submitted
A row hammer preventing circuitry including: a first table storing a count value representing a hit count and an address bit of multiple entries, each entry corresponding to access-requested target rows; a second table including safe bits and a safe bit counter; and a row hammer preventing logic to identify masking entries, on which a masking comparison is to be performed, among the entries on the basis of the safe bit counter, to determine a hit or miss on the basis of whether other bits except an MSB among address bits of an access-requested target row match other bits except an MSB among address bits of the masking entries, and to generate a control signal indicating an additional refresh on rows adjacent to rows corresponding to a masking entry whose hit count is greater than a threshold value.
