17938898. ERROR DETECTION AND CLASSIFICATION AT A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
Contents
- 1 ERROR DETECTION AND CLASSIFICATION AT A MEMORY DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 ERROR DETECTION AND CLASSIFICATION AT A MEMORY DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
ERROR DETECTION AND CLASSIFICATION AT A MEMORY DEVICE
Organization Name
Inventor(s)
Aaron P. Boehm of Boise ID (US)
Scott E. Schaefer of Boise ID (US)
ERROR DETECTION AND CLASSIFICATION AT A MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17938898 titled 'ERROR DETECTION AND CLASSIFICATION AT A MEMORY DEVICE
Simplified Explanation
Methods, systems, and devices for error detection and classification are described in the patent application. A memory device reads a codeword from memory, generates syndrome bits, and uses them to detect errors in the codeword. The memory device then provides error detection bits to a host device.
- Memory device reads codeword from memory
- Generates first set of syndrome bits
- Uses first set of syndrome bits to generate first error detection bit
- Generates second set of syndrome bits
- Uses second set of syndrome bits to generate second error detection bit
- Provides error detection bits to host device
Potential Applications
This technology can be applied in:
- Data storage systems
- Communication systems
- Error correction algorithms
Problems Solved
- Error detection in memory devices
- Efficient classification of errors
- Improved data reliability
Benefits
- Enhanced data integrity
- Increased system reliability
- Faster error detection and correction
Potential Commercial Applications
- Memory devices
- Data centers
- Communication networks
Possible Prior Art
One possible prior art for error detection and classification in memory devices is the use of parity bits to detect errors in data transmission.
Unanswered Questions
How does this technology compare to existing error detection methods?
The article does not provide a comparison with existing error detection methods to highlight the advantages of this technology.
What are the potential limitations of this error detection and classification system?
The article does not address any potential limitations or challenges that may arise when implementing this technology.
Original Abstract Submitted
Methods, systems, and devices for error detection and classification are described. A memory device may read a codeword from a memory and generate a first set of syndrome bits for the codeword. The memory device may use the first set of syndrome bits to generate a first error detection bit. The memory device may generate a second set of syndrome bits for the codeword and use the second set of syndrome bits to generate a second error detection bit. The memory device may provide the first error detection bit and the second error detection bit to a host device.
