17937473. SEMICONDUCTOR DEVICE WITH CMOS INVERTER simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR DEVICE WITH CMOS INVERTER
Organization Name
Inventor(s)
SEMICONDUCTOR DEVICE WITH CMOS INVERTER - A simplified explanation of the abstract
This abstract first appeared for US patent application 17937473 titled 'SEMICONDUCTOR DEVICE WITH CMOS INVERTER
Simplified Explanation
The patent application describes a semiconductor device that includes a buried insulation layer pattern on a lower substrate. It also includes a first and second semiconductor pattern on the buried insulation layer pattern. A lower conductive pattern is formed in a recess between the first and second semiconductor patterns, and a common gate structure fills the remaining portion of the recess.
- The first semiconductor pattern includes a first impurity region, a first channel region, and a second impurity region stacked from the upper surface towards the lower substrate.
- The second semiconductor pattern includes a third impurity region, a second channel region, and a fourth impurity region.
Potential applications of this technology:
- Integrated circuits
- Microprocessors
- Memory devices
Problems solved by this technology:
- Improved performance and efficiency of semiconductor devices
- Enhanced integration of components on a single chip
Benefits of this technology:
- Higher speed and lower power consumption
- Increased functionality and miniaturization of devices
- Improved reliability and manufacturing yield
Original Abstract Submitted
A semiconductor device includes a buried insulation layer pattern on a lower substrate. A first semiconductor pattern and a second semiconductor pattern pattern are disposed on on the buried insulation layer pattern. A lower conductive pattern is formed in a lower portion of a first recess between the first and second semiconductor patterns, and the lower conductive pattern may contact lower sidewalls of the first and second semiconductor patterns. A common gate structure formed on the lower conductive pattern fills a remaining portion of the first recess. The first semiconductor pattern may include a first impurity region, a first channel region, and a second impurity region sequentially stacked from an upper surface of the first semiconductor towards the lower substrate. The second semiconductor pattern includes a third impurity region, a second channel region, and a fourth impurity region.
