17937431. POWER GATING DUMMY POWER TRANSISTORS FOR BACK SIDE POWER DELIVERY NETWORKS simplified abstract (International Business Machines Corporation)

POWER GATING DUMMY POWER TRANSISTORS FOR BACK SIDE POWER DELIVERY NETWORKS

Organization Name

International Business Machines Corporation

Inventor(s)

Tao Li of Slingerlands NY (US)

Ruilong Xie of Niskayuna NY (US)

Kangguo Cheng of Schenectady NY (US)

POWER GATING DUMMY POWER TRANSISTORS FOR BACK SIDE POWER DELIVERY NETWORKS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17937431 titled 'POWER GATING DUMMY POWER TRANSISTORS FOR BACK SIDE POWER DELIVERY NETWORKS

Simplified Explanation

The semiconductor chip device described in the abstract includes a power delivery network on the backside of the substrate, with dummy transistors and a power gating transistor used to transfer power to the analog or digital circuit elements.

• The device utilizes a backside power delivery network for efficient power transfer.
• Dummy transistors are strategically placed in the circuit to optimize power distribution.
• A power gating transistor controls the transfer of power from the dummy transistors to the functional circuit elements.
• By using the backside power delivery network, more space is available on the front side for functional devices.

Potential Applications

This technology could be applied in various semiconductor devices where efficient power delivery is crucial, such as mobile devices, IoT devices, and automotive electronics.

Problems Solved

1. Efficient power distribution within a semiconductor chip device. 2. Maximizing the use of space on the front side of the substrate for functional devices.

Benefits

1. Improved power efficiency. 2. Enhanced performance of analog or digital circuit elements. 3. Space optimization for functional devices.

Potential Commercial Applications

"Efficient Power Delivery in Semiconductor Devices: Applications and Benefits"

Possible Prior Art

There may be prior art related to power delivery networks in semiconductor devices, but specific examples are not provided in this context.

How does this technology impact the overall power consumption of the semiconductor chip device?

The abstract does not specify the potential impact on power consumption efficiency with the implementation of this technology. Further research or testing may be needed to determine the exact effects.

Are there any limitations to the size or scale of semiconductor devices that can benefit from this technology?

The abstract does not mention any limitations regarding the size or scale of semiconductor devices that can utilize this technology. It would be important to investigate whether there are any constraints in applying this innovation to different types of devices.

Original Abstract Submitted

A semiconductor chip device includes a substrate with a back end of line layer and a backside power delivery network. An input power line is electrically coupled to the backside power delivery network. Dummy transistors are positioned in a circuit with analog or digital circuit elements. A power gating transistor is positioned in the circuit between the dummy transistors and the analog or digital circuit elements. Power from the power input line is provided from the backside power delivery network, through the dummy transistors, and controlled by the power gating transistor for transfer to the analog or digital circuit elements. The device uses a backside delivery of power to the area of the dummy transistors to transfer power into the analog or digital circuit elements, which leaves more of the front side footprint for functional devices.