17937313. POWER VIA WITH REDUCED RESISTANCE simplified abstract (ADVANCED MICRO DEVICES, INC.)
Contents
- 1 POWER VIA WITH REDUCED RESISTANCE
POWER VIA WITH REDUCED RESISTANCE
Organization Name
Inventor(s)
Richard T. Schultz of Fort Collins CO (US)
POWER VIA WITH REDUCED RESISTANCE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17937313 titled 'POWER VIA WITH REDUCED RESISTANCE
Simplified Explanation
The abstract describes an apparatus and method for efficiently routing power signals across a semiconductor die by using micro through silicon vias (TSVs) that connect different nodes on the die.
- The integrated circuit includes micro TSVs that traverse through a silicon substrate layer to a backside metal layer, providing power connection redundancy and improving charge sharing.
- A power rail connects the micro TSVs, replacing contacts between the TSVs and a frontside metal layer, which reduces voltage droop and improves wafer yield.
Potential Applications
This technology could be applied in various semiconductor devices where efficient power routing is crucial, such as microprocessors, memory chips, and other integrated circuits.
Problems Solved
This innovation addresses the challenge of efficiently routing power signals across a semiconductor die, improving charge sharing, wafer yield, and reducing voltage droop.
Benefits
The use of micro TSVs and power rails increases power connection redundancy, leading to improved performance, reliability, and efficiency in semiconductor devices.
Potential Commercial Applications
This technology could be valuable in the semiconductor industry for enhancing the power distribution efficiency in various electronic devices, potentially leading to more reliable and high-performance products.
Possible Prior Art
Prior art in the field of semiconductor technology may include methods for power distribution and routing across a die, but the specific approach of using micro TSVs and power rails for improved power connection redundancy may be a novel aspect of this innovation.
Unanswered Questions
How does this technology impact the overall power consumption of the semiconductor device?
The abstract does not provide information on how this technology affects the power consumption of the semiconductor device. Further research or testing may be needed to determine the impact on power efficiency.
What are the potential challenges or limitations of implementing this technology in large-scale production?
The abstract does not address the potential challenges or limitations of implementing this technology in large-scale production. Factors such as cost, scalability, and compatibility with existing manufacturing processes could be important considerations that need to be explored further.
Original Abstract Submitted
An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes, at a first node that receives a power supply reference, a first micro through silicon via (TSV) that traverses through a silicon substrate layer to a backside metal layer. The integrated circuit includes, at a second node that receives the power supply reference, a second micro TSV that physically contacts at least one source region. The integrated circuit includes a first power rail that connects the first micro TSV to the second micro TSV. This power rail replaces contacts between the micro TSVs and a second power rail such as the frontside metal zero (M0) layer. Each of the first power rail, the second power rail, and the backside metal layer provides power connection redundancy that increases charge sharing, improves wafer yield, and reduces voltage droop.
