HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT

The apparatus disclosed in the patent application is designed to facilitate hardware enhancements for double precision systolic support. It includes matrix acceleration hardware with double-precision matrix multiplication circuitry, adders, an accumulator circuit, and a down conversion and rounding circuit.

Matrix acceleration hardware with double-precision (DP) matrix multiplication circuitry
Multiplier circuits to multiply pairs of input source operands in a DP floating-point format
Adders to accumulate the multiplier outputs in a high precision intermediate format
Accumulator circuit to accumulate adder outputs with global source operands or intermediate results
Down conversion and rounding circuit to convert and round the final result in the DP floating-point format

Potential Applications

This technology can be applied in high-performance computing systems, scientific simulations, financial modeling, and machine learning algorithms that require double-precision calculations.

Problems Solved

This innovation addresses the need for efficient hardware support for double-precision matrix multiplication, which is crucial for complex mathematical operations in various fields.

Benefits

The apparatus improves the speed and accuracy of double-precision calculations, leading to faster processing times and more precise results in numerical computations.

Potential Commercial Applications

Potential commercial applications include supercomputers, data centers, AI accelerators, and other high-performance computing systems that require double-precision matrix multiplication capabilities.

Possible Prior Art

One possible prior art for this technology could be existing hardware accelerators for single-precision matrix multiplication, which may not provide the same level of precision and efficiency for double-precision calculations.

Unanswered Questions

How does this technology compare to existing solutions for double-precision matrix multiplication?

This article does not provide a direct comparison with existing solutions in terms of performance, efficiency, or cost-effectiveness.

What are the specific technical specifications and requirements for implementing this apparatus in different hardware systems?

The article does not delve into the specific technical details or compatibility considerations for integrating this apparatus into various hardware configurations.

Original Abstract Submitted

An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.

17937252. HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT simplified abstract (Intel Corporation)

Contents

HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT

Organization Name

Inventor(s)