17936959. METHOD FOR FORMING PACKAGE STRUCTURE WITH CAVITY SUBSTRATE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
METHOD FOR FORMING PACKAGE STRUCTURE WITH CAVITY SUBSTRATE
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Po-Hao Tsai of Taoyuan City (TW)
Ming-Da Cheng of Taoyuan City (TW)
Mirng-Ji Lii of Sinpu Township (TW)
METHOD FOR FORMING PACKAGE STRUCTURE WITH CAVITY SUBSTRATE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17936959 titled 'METHOD FOR FORMING PACKAGE STRUCTURE WITH CAVITY SUBSTRATE
Simplified Explanation
The patent application describes a method for forming a package structure that includes etching a substrate to create a cavity and thermal vias underneath it. The method also involves placing an electronic device in the cavity, which is thermally connected to the thermal vias. An encapsulating material is then formed in the cavity, covering the electronic device. Additionally, an insulating layer with an RDL structure is formed over the encapsulating material, providing electrical connection to the electronic device.
- Etching a substrate to create a cavity and thermal vias underneath it
- Placing an electronic device in the cavity, which is thermally connected to the thermal vias
- Forming an encapsulating material in the cavity, covering the electronic device
- Forming an insulating layer with an RDL structure over the encapsulating material, providing electrical connection to the electronic device
Potential Applications
- Electronics packaging
- Semiconductor devices
- Integrated circuits
Problems Solved
- Efficient thermal management in electronic devices
- Protection and encapsulation of electronic components
Benefits
- Improved thermal performance
- Enhanced protection for electronic devices
- Efficient electrical connection through the RDL structure
Original Abstract Submitted
A method for forming a package structure is provided. The method includes etching a top surface of a substrate to form a cavity. The substrate includes thermal vias directly under a bottom surface of the cavity. The method also includes forming at least one first electronic device in the cavity of the substrate. The first electronic device is thermally coupled to the thermal vias. The method further includes forming an encapsulating material in the cavity, so that the encapsulating material extends along sidewalls of the first electronic device and covers a surface of the first electronic device opposite the bottom surface of the cavity. In Addition, the method includes forming an insulating layer having an RDL structure over the encapsulating material. The RDL structure is electrically connected to the first electronic device.
