17936937. PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Organization Name
Inventor(s)
Beoungjun Choi of Sejong-si (KR)
PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17936937 titled 'PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Simplified Explanation
The patent application describes a package substrate and a semiconductor package that includes the substrate. The semiconductor package consists of a package substrate with a base, front and back sides, rear pads, lower connection patterns, and front pads. It also includes a first support pattern with a greater thickness than the front pads, and a protective insulating layer with openings exposing the front pads and the first support pattern. The package further includes a lower semiconductor chip on the protective insulating layer, spaced apart from the first support pattern, and a first upper semiconductor chip vertically overlapping the lower chip and the first support pattern.
- The patent application describes a package substrate and semiconductor package design.
- The package substrate includes a base with front and back sides, rear pads, lower connection patterns, and front pads.
- A first support pattern with a greater thickness than the front pads is included on the front side of the base.
- The protective insulating layer on the front side of the base has openings exposing the front pads and the first support pattern.
- The semiconductor package includes a lower semiconductor chip on the protective insulating layer, spaced apart from the first support pattern.
- A first upper semiconductor chip is vertically overlapped with the lower chip and the first support pattern.
Potential Applications
The technology described in this patent application can be applied in various semiconductor packaging applications, including:
- Integrated circuits
- Microprocessors
- Memory devices
- Power devices
- Communication devices
Problems Solved
The described technology addresses several problems in semiconductor packaging, such as:
- Ensuring proper electrical connections between different components of the package substrate.
- Providing support and protection for the semiconductor chips.
- Reducing the overall size and thickness of the semiconductor package.
- Enhancing the reliability and performance of the package.
Benefits
The technology described in the patent application offers several benefits, including:
- Improved electrical connectivity and signal transmission within the semiconductor package.
- Enhanced support and protection for the semiconductor chips, reducing the risk of damage.
- Compact design, allowing for smaller and thinner semiconductor packages.
- Increased reliability and performance of the package, leading to improved overall device performance.
Original Abstract Submitted
A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.
