17936494. VICTIM ROW COUNTERS IN MEMORY DEVICES simplified abstract (HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP)
Contents
- 1 VICTIM ROW COUNTERS IN MEMORY DEVICES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 VICTIM ROW COUNTERS IN MEMORY DEVICES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
VICTIM ROW COUNTERS IN MEMORY DEVICES
Organization Name
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor(s)
Melvin K. Benedict of Magnolia TX (US)
Eric L. Pope of Tomball TX (US)
VICTIM ROW COUNTERS IN MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17936494 titled 'VICTIM ROW COUNTERS IN MEMORY DEVICES
Simplified Explanation
The memory device described in the patent application includes victim counters and aggressor counters associated with rows of memory cells. The victim counters advance in response to increases in counts of aggressor counters from neighboring rows of memory cells.
- Memory device with rows of memory cells
- Victim counters associated with rows
- Aggressor counters associated with rows
- Victim counters advance in response to aggressor counters from neighboring rows
Potential Applications
The technology described in the patent application could be applied in:
- Memory management systems
- Cache memory systems
- Error correction systems
Problems Solved
The technology addresses issues such as:
- Memory cell interference
- Data corruption in memory systems
- Efficient memory access
Benefits
The benefits of this technology include:
- Improved memory performance
- Enhanced data integrity
- Reduced memory errors
Potential Commercial Applications
This technology could be utilized in various commercial applications such as:
- Computer systems
- Mobile devices
- Data centers
Possible Prior Art
One possible prior art related to this technology is:
- Memory management techniques in computer systems
Unanswered Questions
How does this technology impact power consumption in memory devices?
The patent application does not provide information on the power consumption implications of this technology. Further research is needed to understand its effects on power usage.
Are there any limitations to the scalability of this technology in large-scale memory systems?
The scalability of this technology in large-scale memory systems is not discussed in the patent application. Additional studies are required to determine any potential limitations in scalability.
Original Abstract Submitted
In some examples, a memory device includes a plurality of rows of memory cells, a plurality of victim counters associated with respective rows of memory cells of the plurality of rows of memory cells, and a plurality of aggressor counters associated with the respective rows of memory cells. A first victim counter of the plurality of counters is associated with a first row of the plurality of rows of memory cells, the first victim counter to advance in response to advances in counts of aggressor counters associated with neighboring rows of memory cells that are neighbors of the first row.
