17936417. MONOLITHIC STACKED FIELD EFFECT TRANSISTOR (SFET) WITH DUAL MIDDLE DIELECTRIC ISOLATION (MDI) SEPARATION simplified abstract (International Business Machines Corporation)

MONOLITHIC STACKED FIELD EFFECT TRANSISTOR (SFET) WITH DUAL MIDDLE DIELECTRIC ISOLATION (MDI) SEPARATION

Organization Name

International Business Machines Corporation

Inventor(s)

Jingyun Zhang of Albany NY (US)

Ruilong Xie of Niskayuna NY (US)

Julien Frougier of Albany NY (US)

Ruqiang Bao of Niskayuna NY (US)

Prabudhya Roy Chowdhury of Albany NY (US)

MONOLITHIC STACKED FIELD EFFECT TRANSISTOR (SFET) WITH DUAL MIDDLE DIELECTRIC ISOLATION (MDI) SEPARATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17936417 titled 'MONOLITHIC STACKED FIELD EFFECT TRANSISTOR (SFET) WITH DUAL MIDDLE DIELECTRIC ISOLATION (MDI) SEPARATION

Simplified Explanation

Embodiments of the present invention involve processing methods for monolithic stacked field effect transistors (SFETs) with dual middle dielectric isolation (MDI) separation. In one example, a first nanosheet is formed, followed by the vertical stacking of a second nanosheet over the first. Gates are then formed around the channel regions of both nanosheets, with a middle dielectric isolation structure created between them. This structure includes two layers of middle dielectric isolation stacked vertically, with a portion of the gate extending between these layers within the structure.

• Formation of first and second nanosheets
• Stacking of nanosheets
• Gate formation around channel regions
• Creation of middle dielectric isolation structure with two layers
• Gate extension between middle dielectric isolation layers

Potential Applications

The technology described in this patent application could be applied in the following areas:

• Advanced semiconductor manufacturing
• High-performance computing
• Nanoelectronics research

Problems Solved

The innovation addresses the following issues:

• Improved isolation between stacked nanosheets
• Enhanced performance and reliability of SFETs
• Increased efficiency in transistor design

Benefits

The technology offers the following benefits:

• Higher transistor density
• Lower power consumption
• Improved overall device performance

Potential Commercial Applications

With its advantages, this technology could find applications in:

• Smartphone processors
• Data center servers
• IoT devices

Possible Prior Art

One possible prior art in this field is the use of traditional dielectric isolation techniques in transistor manufacturing processes.

How does this technology compare to existing methods for isolating stacked nanosheets in SFETs?

The article does not provide a direct comparison between this technology and existing methods for isolating stacked nanosheets in SFETs.

What are the specific challenges faced in implementing dual middle dielectric isolation separation in SFETs?

The article does not delve into the specific challenges faced in implementing dual middle dielectric isolation separation in SFETs.

Original Abstract Submitted

Embodiments of the present invention are directed to monolithic stacked field effect transistor (SFET) processing methods and resulting structures having dual middle dielectric isolation (MDI) separation. In a non-limiting embodiment of the invention, a first nanosheet is formed and a second nanosheet is vertically stacked over the first nanosheet. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet and a middle dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The middle dielectric isolation structure includes a first middle dielectric isolation layer and a second middle dielectric isolation layer vertically stacked over the first middle dielectric isolation layer. A portion of the gate extends between the first middle dielectric isolation layer and the second middle dielectric isolation layer in the middle dielectric isolation structure.