17935122. STORAGE DEVICE USING WAFER-TO-WAFER BONDING AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

STORAGE DEVICE USING WAFER-TO-WAFER BONDING AND METHOD OF MANUFACTURING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

YOUNGGUL Song of Hwaseong-Si (KR)

Junyeong Seok of Seoul (KR)

Eun Chu Oh of Hwaseong-si (KR)

Byungchul Jang of Suwon-si (KR)

STORAGE DEVICE USING WAFER-TO-WAFER BONDING AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17935122 titled 'STORAGE DEVICE USING WAFER-TO-WAFER BONDING AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The abstract describes a storage device that includes a non-volatile memory device with a three-dimensional (3D) memory cell array. The memory device is formed by vertically stacking and bonding two substrates, with the first substrate containing a row decoder and the second substrate containing a page buffer unit and the memory cell array.

• The storage device includes a non-volatile memory device with a 3D memory cell array.
• The memory cell array is formed by stacking and bonding two substrates.
• The first substrate contains a row decoder for selecting word lines.
• The second substrate contains a page buffer unit for selecting bit lines.
• The memory cell array is located between the first and second substrates.

Potential applications of this technology:

• Data storage devices such as solid-state drives (SSDs) and memory cards.
• Mobile devices like smartphones and tablets.
• Cloud storage systems and data centers.

Problems solved by this technology:

• Increased storage capacity by utilizing a 3D memory cell array.
• Efficient selection of word lines and bit lines using the row decoder and page buffer unit.
• Compact design by vertically stacking and bonding the substrates.

Benefits of this technology:

• Higher storage density and capacity.
• Faster data access and retrieval.
• Reduced power consumption.
• Compact and space-saving design.

Original Abstract Submitted

A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.