17934298. SEMICONDUCTOR PACKAGES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGES
Organization Name
Inventor(s)
Seungduk Baek of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17934298 titled 'SEMICONDUCTOR PACKAGES
Simplified Explanation
The abstract describes a semiconductor package that includes two semiconductor chips. The first chip has a bonding pad on its top surface and a penetration via on its bottom surface, which goes through the chip. The second chip has an interconnection pattern on its bottom surface and a bonding pad directly bonded to the first chip's bonding pad. The width of the penetration via is smaller than the bonding pad, while the width of the interconnection pattern is larger than the bonding pad.
- The semiconductor package includes two semiconductor chips.
- The first chip has a bonding pad on its top surface and a penetration via on its bottom surface.
- The second chip has an interconnection pattern on its bottom surface and a bonding pad directly bonded to the first chip's bonding pad.
- The width of the penetration via is smaller than the bonding pad.
- The width of the interconnection pattern is larger than the bonding pad.
Potential Applications
- Semiconductor packaging industry
- Electronics manufacturing
Problems Solved
- Simplifies the bonding process between semiconductor chips
- Allows for direct bonding of bonding pads
Benefits
- Improved efficiency in semiconductor packaging
- Enhanced electrical connectivity between chips
Original Abstract Submitted
A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.
