17933557. QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING simplified abstract (International Business Machines Corporation)
Contents
- 1 QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING
Organization Name
International Business Machines Corporation
Inventor(s)
Michael Sperling of Poughkeepsie NY (US)
Daniel Mark Dreps of Georgetown TX (US)
Erik English of Salt Point NY (US)
QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17933557 titled 'QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING
Simplified Explanation
The integrated circuit communication architecture described in the patent application includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane sends a clock signal from one chip to another, the clock divider on the receiving chip divides the clock signal into two reduced-rate signals, and the de-skew circuit processes these signals for data sampling.
- Clock lane sends clock signal from one chip to another
- Clock divider on receiving chip divides signal into reduced-rate signals
- De-skew circuit processes signals for data sampling
Potential Applications
The technology could be applied in various communication systems where precise clock synchronization is required, such as high-speed data transmission between chips in electronic devices.
Problems Solved
This technology solves the problem of clock skew between chips in an integrated circuit, ensuring accurate data sampling and communication between components.
Benefits
The architecture allows for efficient and reliable data transmission between chips, maintaining signal integrity and reducing the risk of errors due to clock misalignment.
Potential Commercial Applications
One potential commercial application of this technology could be in the development of high-performance computing systems, where fast and accurate data transfer is essential for optimal operation.
Possible Prior Art
Prior art in clock synchronization and data sampling techniques may exist, but specific examples are not provided in the patent application.
Unanswered Questions
How does this architecture handle clock signal variations between chips?
The patent application does not detail how the clock divider compensates for any variations in the clock signal between the chips.
What is the power consumption of this integrated circuit communication architecture?
The power consumption of the architecture is not discussed in the patent application, leaving uncertainty about its energy efficiency compared to other solutions.
Original Abstract Submitted
An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.
