17900639. Performance Optimization By Sizing Gates And Source/Drain Contacts Differently For Different Transistors simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Performance Optimization By Sizing Gates And Source/Drain Contacts Differently For Different Transistors
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Li-Hui Chen of Hsinchu County (TW)
Chun-Hung Chen of Hsinchu (TW)
Jhon Jhy Liaw of Hsinchu County (TW)
Performance Optimization By Sizing Gates And Source/Drain Contacts Differently For Different Transistors - A simplified explanation of the abstract
This abstract first appeared for US patent application 17900639 titled 'Performance Optimization By Sizing Gates And Source/Drain Contacts Differently For Different Transistors
Simplified Explanation
The abstract describes a patent application for a first transistor and a second transistor with different dimensions in a lateral direction.
- The first transistor includes a first gate, a first source/drain, and a first source/drain contact.
- The first gate and the first source/drain contact have different dimensions in the lateral direction.
- The second transistor includes a second gate, a second source/drain, and a second source/drain contact.
- The second gate and the second source/drain contact also have different dimensions in the lateral direction.
- The ratios of dimensions in the first transistor are different from the ratios in the second transistor.
- Potential Applications:**
- Semiconductor industry for improving transistor performance.
- Electronics industry for enhancing device efficiency.
- Problems Solved:**
- Inconsistencies in transistor design.
- Limitations in transistor performance due to uniform dimensions.
- Benefits:**
- Improved transistor efficiency.
- Enhanced device performance.
- Potential for new design possibilities in electronics.
Original Abstract Submitted
A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.
