17900001. SEMICONDUCTOR STRUCTURE WITH REDUCED PARASITIC CAPACITANCE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
SEMICONDUCTOR STRUCTURE WITH REDUCED PARASITIC CAPACITANCE AND METHOD FOR MANUFACTURING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Cheng-Ting Chung of Hsinchu (TW)
SEMICONDUCTOR STRUCTURE WITH REDUCED PARASITIC CAPACITANCE AND METHOD FOR MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17900001 titled 'SEMICONDUCTOR STRUCTURE WITH REDUCED PARASITIC CAPACITANCE AND METHOD FOR MANUFACTURING THE SAME
Simplified Explanation
The semiconductor structure described in the patent application includes two source/drain features, at least one channel feature, a gate dielectric layer, a gate feature, and an electrically conductive capping feature.
- The structure has two source/drain features spaced apart from each other.
- There is at least one channel feature between the two source/drain features.
- A gate dielectric layer is on the channel feature.
- A gate feature is on the gate dielectric layer, with a first surface, a second surface, and an interconnect surface.
- An electrically conductive capping feature is in direct contact with one of the surfaces of the gate feature and extends beyond the interconnect surface.
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- Potential Applications
- Semiconductor devices
- Integrated circuits
- Microprocessors
- Problems Solved
- Improving performance and efficiency of semiconductor devices
- Enhancing conductivity and reliability of gate features
- Benefits
- Increased speed and functionality of electronic devices
- Enhanced durability and longevity of semiconductor structures
- Improved overall performance of integrated circuits
Original Abstract Submitted
A semiconductor structure includes two source/drain features spaced apart from each other, at least one channel feature disposed between the two source/drain features, a gate dielectric layer disposed on the at least one channel feature, a gate feature, and an electrically conductive capping feature. The gate feature is disposed on the gate dielectric layer and has a first surface, a second surface which is opposite to the first surface, and an interconnect surface which interconnects the first and second surfaces. The electrically conductive capping feature is in direct contact with one of the first and second surfaces of the gate feature, and extends beyond the interconnect surface of the gate feature. Methods for manufacturing the semiconductor structure are also disclosed.
