17899883. PARALLEL-TO-SERIAL INTERFACE CIRCUIT AND TRANSMISSION DEVICE HAVING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
PARALLEL-TO-SERIAL INTERFACE CIRCUIT AND TRANSMISSION DEVICE HAVING THE SAME
Organization Name
Inventor(s)
Woochul Jung of Hwaseong-si (KR)
Junghwan Choi of Hwaseong-si (KR)
PARALLEL-TO-SERIAL INTERFACE CIRCUIT AND TRANSMISSION DEVICE HAVING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17899883 titled 'PARALLEL-TO-SERIAL INTERFACE CIRCUIT AND TRANSMISSION DEVICE HAVING THE SAME
Simplified Explanation
The abstract describes a parallel-to-serial interface circuit that includes an equalizer, a parallel-to-serial converter, and a driver.
- The equalizer delays odd and even data by a half period and generates pre data, main data, and post data for both odd and even inputs.
- The parallel-to-serial converter selects and combines the pre data, inverted main data, and post data in an alternating sequence to generate the final serial output.
- The driver then drives the pre data, inverted main data, and post data to generate specific voltage levels for each.
Potential Applications
- This technology can be used in various communication systems that require parallel-to-serial conversion, such as data transmission over long distances.
- It can be implemented in high-speed serial interfaces, such as USB, Ethernet, or HDMI, to improve data transfer efficiency.
Problems Solved
- The circuit solves the problem of converting parallel data to serial data while maintaining synchronization and minimizing data distortion.
- It addresses the issue of signal degradation and timing misalignment that can occur during parallel-to-serial conversion.
Benefits
- The equalizer helps to compensate for signal distortion and delay, ensuring accurate data transmission.
- The parallel-to-serial converter efficiently combines the different data components, reducing the complexity of the circuit.
- The driver ensures proper voltage levels for each data component, improving signal integrity and reducing errors.
Original Abstract Submitted
A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.
