17899564. FREQUENCY DIVIDER FOR NON-OVERLAPPING CLOCK SIGNALS simplified abstract (QUALCOMM Incorporated)
FREQUENCY DIVIDER FOR NON-OVERLAPPING CLOCK SIGNALS
Organization Name
Inventor(s)
Nagarjuna Nallam of Bangalore (IN)
FREQUENCY DIVIDER FOR NON-OVERLAPPING CLOCK SIGNALS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17899564 titled 'FREQUENCY DIVIDER FOR NON-OVERLAPPING CLOCK SIGNALS
Simplified Explanation
- A frequency divider is described in the patent application. - The frequency divider includes multiple latches for dividing an input clock by an integer frequency divisor N of three or greater. - Each latch is connected to a pair of logic gates, with one gate controlling the setting of the latch and the other gate controlling the resetting of the latch. - The latches output overlapping clock signals that are divided in frequency with a 50% duty cycle. - The logic gates process the overlapping clock signals and the input clock signal to provide non-overlapping clock signals with the same frequency as the overlapping signals but with a duty cycle of 50/N%.
Potential Applications
- Frequency division in electronic circuits - Clock signal generation in digital systems - Synchronization of multiple devices
Problems Solved
- Efficient frequency division - Generation of non-overlapping clock signals - Simplified control of clock signals
Benefits
- Precise frequency division - 50% duty cycle for clock signals - Simplified design and implementation in electronic systems
Original Abstract Submitted
A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.
