17897648. SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THEREOF

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Ming-Fa Chen of Hsinchu City (TW)

Yun-Han Lee of Hsinchu (TW)

Lee-Chung Lu of Hsinchu (TW)

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17897648 titled 'SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THEREOF

Simplified Explanation

The semiconductor device described in the abstract includes a first chip, a second chip, and an interposer bonded to both chips, with power rails to deliver power to the chips.

  • The semiconductor device consists of a first chip with device features and interconnect structures, a second chip with device features and interconnect structures, and an interposer.
  • The interposer is bonded to the first and second chips and contains power rails to deliver power to both chips.
  • The interposer is located on the opposite side of the device features compared to the interconnect structures on the first and second chips.

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      1. Potential Applications of this Technology
  • High-performance computing systems
  • Data centers
  • Telecommunications equipment
      1. Problems Solved by this Technology
  • Efficient power delivery to multiple chips in a semiconductor device
  • Improved performance and reliability of the overall system
      1. Benefits of this Technology
  • Enhanced power distribution capabilities
  • Increased efficiency in power delivery
  • Improved overall system performance and reliability


Original Abstract Submitted

A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.