17896919. STAIRCASE FORMATION IN A MEMORY ARRAY simplified abstract (Micron Technology, Inc.)
Contents
STAIRCASE FORMATION IN A MEMORY ARRAY
Organization Name
Inventor(s)
Alyssa N. Scarbrough of Boise ID (US)
Jordan D. Greenlee of Boise ID (US)
STAIRCASE FORMATION IN A MEMORY ARRAY - A simplified explanation of the abstract
This abstract first appeared for US patent application 17896919 titled 'STAIRCASE FORMATION IN A MEMORY ARRAY
Simplified Explanation
The abstract describes methods, systems, and devices for staircase formation in a memory array.
- A liner made of a first liner material is deposited on a tread, with a first portion of the liner being doped.
- The second portion of the liner is converted into a second liner material using a chemical process after doping the first portion.
- The first portion of the liner material is removed to expose a first sub-tread, followed by the removal of the second portion to expose a second sub-tread.
Potential Applications:
- Memory array fabrication
- Semiconductor manufacturing
Problems Solved:
- Efficient staircase formation in a memory array
- Improved performance and reliability of memory devices
Benefits:
- Enhanced memory array functionality
- Increased efficiency in memory array fabrication
- Improved overall performance of memory devices
Original Abstract Submitted
Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.
