17896797. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Seungmin Kim of Asan-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17896797 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The abstract describes a semiconductor package that includes a package substrate, lower and upper wiring layers, a solder resist layer, a semiconductor chip, and a mold part. The package substrate has a lower surface, an upper surface, and a land region. The lower wiring layer is on the lower surface and connected to the upper wiring layer. The solder resist layer on the lower surface has an opening exposing the land region. The semiconductor chip is on the package substrate and has contact pads connected to the upper wiring layer. The mold part is on the package substrate. The package substrate also has an open region on its bottom surface, adjacent to at least one edge, where the solder resist layer is not present.

  • The semiconductor package includes a package substrate with lower and upper wiring layers, a solder resist layer, a semiconductor chip, and a mold part.
  • The lower wiring layer is on the lower surface of the package substrate and connected to the upper wiring layer.
  • The solder resist layer on the lower surface has an opening exposing the land region.
  • The semiconductor chip is on the package substrate and has contact pads connected to the upper wiring layer.
  • The mold part is on the package substrate.
  • The package substrate has an open region on its bottom surface, adjacent to at least one edge, where the solder resist layer is not present.

Potential Applications

  • Semiconductor packaging industry
  • Electronics manufacturing

Problems Solved

  • Provides a simplified and efficient design for a semiconductor package
  • Allows for better electrical connections between the semiconductor chip and the package substrate

Benefits

  • Improved performance and reliability of semiconductor packages
  • Simplified manufacturing process
  • Enhanced electrical connectivity between components


Original Abstract Submitted

A semiconductor package includes a package substrate including a substrate body having a lower surface and a upper surface, a lower wiring layer on the lower surface and including a land region, an upper wiring layer on the upper surface and electrically connected to the lower wiring layer, and a solder resist layer on the lower surface and including an opening exposing the land region. The semiconductor package further includes a semiconductor chip on the package substrate and having contact pads electrically connected to the upper wiring layer, and a mold part on the package substrate, wherein the package substrate further includes an open region defined by a portion of a bottom surface of the package substrate on which the solder resist layer is not present and that is adjacent to at least one edge of the package substrate on the bottom surface of the package substrate.