17895047. SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

From WikiPatents
Jump to navigation Jump to search

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Tseng Hsing Lin of Hsinchu City (TW)

Chien-Hsun Lee of Hsin-chu County (TW)

Tsung-Ding Wang of Tainan (TW)

Jung-Wei Cheng of Hsinchu City (TW)

Hao-Cheng Hou of Hsinchu City (TW)

Sheng-Chi Lin of Yilan County (TW)

Jeng-An Wang of Hsinchu City (TW)

Yao-Cheng Wu of Changhua County (TW)

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17895047 titled 'SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

Simplified Explanation

The patent application describes a method for forming metal patterns and test patterns on a package region using multiple polymer layers.

  • A first polymer layer is formed across a package region and a test region.
  • A first metal pattern is formed in the package region, with an upper portion on the first polymer layer and a lower portion penetrating through it.
  • A first test pattern is simultaneously formed in the test region on the first polymer layer, with a first opening exposing the layer.
  • A second polymer layer is formed on the first metal pattern in the package region.
  • A second test pattern is simultaneously formed on the first test pattern in the test region, with a third opening larger than the first opening.

Potential applications of this technology:

  • Semiconductor packaging
  • Microelectronics manufacturing
  • Integrated circuit testing

Problems solved by this technology:

  • Efficient formation of metal patterns and test patterns
  • Improved reliability and performance of electronic devices

Benefits of this technology:

  • Enhanced functionality of electronic components
  • Increased productivity in manufacturing processes
  • Cost-effective production of integrated circuits


Original Abstract Submitted

A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.