17894057. PACKAGE COMPRISING A CHIPLET LOCATED BETWEEN TWO METALLIZATION PORTIONS simplified abstract (QUALCOMM Incorporated)

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PACKAGE COMPRISING A CHIPLET LOCATED BETWEEN TWO METALLIZATION PORTIONS

Organization Name

QUALCOMM Incorporated

Inventor(s)

Yanmei Song of San Diego CA (US)

William Stone of San Diego CA (US)

Jianwen Xu of San Diego CA (US)

John Holmes of Escondido CA (US)

Ryan Lane of San Diego CA (US)

PACKAGE COMPRISING A CHIPLET LOCATED BETWEEN TWO METALLIZATION PORTIONS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17894057 titled 'PACKAGE COMPRISING A CHIPLET LOCATED BETWEEN TWO METALLIZATION PORTIONS

Simplified Explanation

The patent application describes a package comprising multiple integrated devices and chiplets interconnected through metallization portions and pillar interconnects.

  • The package includes a first metallization portion.
  • A first integrated device is coupled to the first metallization portion.
  • A second integrated device is also coupled to the first metallization portion.
  • A second metallization portion is connected to the first metallization portion through a first plurality of pillar interconnects.
  • A first chiplet is located between the first and second metallization portions, electrically coupled to the first integrated device.
  • A second chiplet is also located between the first and second metallization portions, electrically coupled to the second integrated device.

Potential applications of this technology:

  • Advanced semiconductor packaging for high-performance computing applications.
  • Integration of multiple devices in a compact and efficient manner.

Problems solved by this technology:

  • Enhanced connectivity and communication between integrated devices and chiplets.
  • Improved performance and functionality of semiconductor packages.

Benefits of this technology:

  • Increased efficiency and speed of data transfer within the package.
  • Compact design for space-saving and improved thermal management.


Original Abstract Submitted

A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion through a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion.

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