17888090. CLOCK FREQUENCY MANAGEMENT OF MULTIPLE CIRCUITRIES simplified abstract (Intel Corporation)

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CLOCK FREQUENCY MANAGEMENT OF MULTIPLE CIRCUITRIES

Organization Name

Intel Corporation

Inventor(s)

Marc Beuchat of Orangevale CA (US)

Eric Samson of Folsom CA (US)

Philip Meyer of Draper UT (US)

Namita Sharma of New Delhi (IN)

Pallavi T J of Bangalore Rural (IN)

CLOCK FREQUENCY MANAGEMENT OF MULTIPLE CIRCUITRIES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17888090 titled 'CLOCK FREQUENCY MANAGEMENT OF MULTIPLE CIRCUITRIES

Simplified Explanation

The patent application describes a system with circuitries that adjust clock frequencies based on temperature and power consumption.

  • First circuitries operate at a first clock frequency
  • Second circuitries operate at a second clock frequency
  • Circuitry adjusts the first and second clock frequencies
  • Target ratio based on temperature and power consumption determines adjustments
  • Target ratio also considers clock frequencies, stall time, and dynamic capacitance

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      1. Potential Applications
  • Mobile devices
  • Internet of Things (IoT) devices
  • Wearable technology
  • Embedded systems
      1. Problems Solved
  • Overheating of devices
  • Power consumption optimization
  • Performance efficiency
      1. Benefits
  • Improved battery life
  • Enhanced device performance
  • Reduced heat generation


Original Abstract Submitted

A system that includes first circuitries to operate at a first clock frequency, second circuitries to operate at a second clock frequency, and circuitry to adjust the first and second clock frequencies. In some examples, the circuitry is to selectively adjust the first and second clock frequencies provided to the respective first circuitries and the second circuitries according to a target ratio based on temperature and power consumption of the first circuitries and the second circuitries, wherein the target ratio is based on clock frequencies of the first circuitries and the second circuitries, stall time of the first circuitries, and dynamic capacitance of the first circuitries and the second circuitries.