17887494. SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Meng-Pei Lu of Hsinchu City (TW)

Shin-Yi Yang of New Taipei City (TW)

Yun-Chi Chiang of Hsinchu City (TW)

Han-Tang Hung of Taipei City (TW)

Cian-Yu Chen of Taichung City (TW)

Ming-Han Lee of Taipei City (TW)

SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17887494 titled 'SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME

Simplified Explanation

The semiconductor structure described in the patent application includes a substrate, gate electrode, source/drain regions, backside contact, dielectric layer, and conductive via.

• The gate electrode is located within the substrate.
• The source/drain regions are positioned in the substrate and are laterally adjacent to the gate electrode.
• The backside contact is situated above the source/drain regions and gate electrode.
• The first dielectric layer is placed between the backside contact and the source/drain regions and gate electrode.
• The conductive via extends through the dielectric layer to connect the source/drain regions and backside contact, and is made of an anisotropic transport material or a topological material.

Potential applications of this technology:

• Semiconductor devices
• Integrated circuits
• Power electronics

Problems solved by this technology:

• Improving electrical connectivity in semiconductor structures
• Enhancing performance and reliability of semiconductor devices

Benefits of this technology:

• Increased efficiency in semiconductor devices
• Enhanced electrical connectivity
• Improved overall performance and reliability

Original Abstract Submitted

A semiconductor structure includes a substrate, at least one gate electrode, a plurality of source/drain (S/D) regions, a backside contact, a first dielectric layer, and a conductive via. The at least one gate electrode is disposed in the substrate. The S/D regions is disposed in the substrate and laterally disposed aside the at least one gate electrode. The backside contact is disposed above the S/D regions and the at least one gate electrode. The first dielectric layer is disposed between the backside contact and the plurality of S/D regions and the at least one gate electrode. The conductive via is extended through the first dielectric layer to electrically connect the S/D regions and the backside contact. The conductive via includes an anisotropic transport material or a topological material.