17887154. MULTI-PORTED REGISTER FILE WITH CFETS simplified abstract (Intel Corporation)

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MULTI-PORTED REGISTER FILE WITH CFETS

Organization Name

Intel Corporation

Inventor(s)

Charles Augustine of Portland OR (US)

Seenivasan Subramaniam of Hillsboro OR (US)

Patrick Morrow of Portland OR (US)

Muhammad M. Khellah of Tigard OR (US)

MULTI-PORTED REGISTER FILE WITH CFETS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17887154 titled 'MULTI-PORTED REGISTER FILE WITH CFETS

Simplified Explanation

The abstract describes an apparatus, system, and method for register file circuits, including designs for 1R1W and 2R1W register files.

  • A register file circuit includes a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor with a source coupled to the WBL, a first inverter with an input connected to the drain of the first PMOS transistor, a second PMOS transistor with a source connected to the output of the first inverter, and a second write bit line (WBLB) coupled to the drain of the second PMOS transistor.

Potential applications of this technology:

  • Computer processors
  • Memory systems
  • Data storage devices

Problems solved by this technology:

  • Efficient data storage and retrieval
  • Improved performance of register file circuits
  • Reduction in power consumption

Benefits of this technology:

  • Faster data access and processing
  • Higher efficiency in computing systems
  • Lower energy consumption and heat generation


Original Abstract Submitted

An apparatus, system, and method for register file circuits are provided. A register file circuit can include a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, a second PMOS transistor including a source coupled to an output of the first inverter, and a second WBL (WBLB) coupled to a drain of the second PMOS transistor. 1R1W register file and 2R1W register file designs are provided.