17886805. VIA ALTERNATE NET SPACING simplified abstract (QUALCOMM Incorporated)
Contents
VIA ALTERNATE NET SPACING
Organization Name
Inventor(s)
Thomas Hua-Min Williams of Irvine CA (US)
Luis Chen of Chula Vista CA (US)
Bed Raj Kandel of San Diego CA (US)
VIA ALTERNATE NET SPACING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17886805 titled 'VIA ALTERNATE NET SPACING
Simplified Explanation
The abstract describes a chip with two nets formed from the same metal layer, with one net neighboring the other. The chip also includes vias on each net, with different spacings between the vias.
- Chip includes two nets formed from the same metal layer
- One net neighbors the other net
- Vias are present on each net
- Different spacings between the vias on the two nets
- Potential Applications:**
- Integrated circuits
- Semiconductor devices
- Electronic components
- Problems Solved:**
- Efficient routing of signals on the chip
- Minimizing interference between neighboring nets
- Improving overall chip performance
- Benefits:**
- Enhanced signal integrity
- Increased chip reliability
- Optimal use of space on the chip
Original Abstract Submitted
A chip includes a first net, and a second net, wherein the first net and the second net are formed from a same metal layer, and the second net neighbors the first net. The chip also includes first vias disposed on the first net, and second vias disposed on the second net. A first spacing is greater than a second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias and the second one of the first vias are adjacent, and the second spacing is between the first one of the first vias and one of the second vias closest to the first one of the first vias.
