17886461. PACKAGE AND FABRICATION METHOD THEREOF simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

From WikiPatents
Jump to navigation Jump to search

PACKAGE AND FABRICATION METHOD THEREOF

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Chih-Wei Wu of Yilan County (TW)

Ying-Ching Shih of Hsinchu City (TW)

Wen-Chih Chiou of Miaoli County (TW)

PACKAGE AND FABRICATION METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17886461 titled 'PACKAGE AND FABRICATION METHOD THEREOF

Simplified Explanation

The patent application describes a package that includes a first molding compound layer, a conductive via embedded in the first molding compound layer, a semiconductor device, a redistribution structure, and a second molding compound layer. The semiconductor device and the redistribution structure are placed on opposite sides of the first molding compound layer, with the semiconductor device being electrically connected to the redistribution structure through the conductive via. The second molding compound layer encapsulates the semiconductor device.

  • The package includes a first molding compound layer.
  • A conductive via is embedded in the first molding compound layer.
  • A semiconductor device and a redistribution structure are placed on opposite sides of the first molding compound layer.
  • The semiconductor device is electrically connected to the redistribution structure through the conductive via.
  • A second molding compound layer encapsulates the semiconductor device.
      1. Potential Applications
  • Integrated circuits
  • Semiconductor packaging
  • Electronic devices
      1. Problems Solved
  • Improved electrical connection between semiconductor device and redistribution structure
  • Enhanced protection and encapsulation of semiconductor device
      1. Benefits
  • Better performance and reliability of electronic devices
  • Increased durability and longevity of semiconductor devices
  • Enhanced functionality and efficiency of integrated circuits


Original Abstract Submitted

A package includes a first molding compound layer, a conductive via embedded in the first molding compound layer, a semiconductor device, a redistribution structure and a second molding compound layer. The semiconductor device and the redistribution structure are respectively disposed on opposite sides of the first molding compound layer, wherein the semiconductor device is electrically connected to the redistribution structure through the conductive via. The second molding compound layer is disposed on the first molding compound layer, wherein the semiconductor device is encapsulated by the second molding compound layer.

Retrieved from "http://wikipatents.org/index.php?title=17886461._PACKAGE_AND_FABRICATION_METHOD_THEREOF_simplified_abstract_(TAIWAN_SEMICONDUCTOR_MANUFACTURING_COMPANY,_LTD.)&oldid=35114"