17886145. SEMICONDUCTOR DEVICE HAVING MIXED CMOS ARCHITECTURE AND METHOD OF MANUFACTURING SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
SEMICONDUCTOR DEVICE HAVING MIXED CMOS ARCHITECTURE AND METHOD OF MANUFACTURING SAME
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Jiann-Tyng Tzeng of Hsinchu (TW)
SEMICONDUCTOR DEVICE HAVING MIXED CMOS ARCHITECTURE AND METHOD OF MANUFACTURING SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17886145 titled 'SEMICONDUCTOR DEVICE HAVING MIXED CMOS ARCHITECTURE AND METHOD OF MANUFACTURING SAME
Simplified Explanation
The semiconductor device described in the patent application includes different cell regions with specific architectures and dopant types for improved performance and functionality.
- The device has first to fourth cell regions, with the first and second cell regions containing pairs of nanosheet stacks with different dopant types (N-type and P-type).
- Each pair of nanosheet stacks represents a CMOS architecture in one direction and CFET architecture in another direction.
- The third and fourth cell regions have CFET architecture and are adjacent to each other.
- The first and second active regions are on corresponding sides of the third and fourth active regions.
- The first and second cell regions are non-CFET cell regions.
Potential applications of this technology:
- Advanced semiconductor devices for improved performance and functionality.
- Enhanced CMOS architecture for better integration and efficiency in electronic devices.
Problems solved by this technology:
- Improved functionality and performance in semiconductor devices.
- Better integration of different architectures for enhanced overall performance.
Benefits of this technology:
- Increased efficiency and functionality in semiconductor devices.
- Enhanced performance and integration capabilities for electronic devices.
Original Abstract Submitted
A semiconductor device (having a CMOS architecture) includes first to fourth cell regions Each of the first and second cell regions includes a pair of first and second stacks of nanosheets relative to, e.g., the Z-axis. The nanosheets of the first stack have a first dopant-type, e.g., N-type. The nanosheets of the second stack have a second dopant type, e.g., P-type. Each pair of first and second stacks represents a CMOS architecture relative to a second direction, e.g., the Y-axis Each of the third and fourth cell regions has CFET architecture, the CFET architecture being a type of CMOS architecture relative to the Z-axis. The third and fourth cell regions are adjacent each other relative to the Y-axis. The first and second active regions are on corresponding first and second sides of each of the third and fourth active regions. The first and second cell regions are non-CFET cell regions.
