17885022. Compliant Pad Spacer for Three-Dimensional Integrated Circuit Package simplified abstract (GOOGLE LLC)
Compliant Pad Spacer for Three-Dimensional Integrated Circuit Package
Organization Name
Inventor(s)
Emad Samadiani of Cypress CA (US)
Padam Jain of San Jose CA (US)
Yingshi Tang of Danville CA (US)
Sue Yun Teng of Belmont CA (US)
Nicholas Chao Wei Wong of San Jose CA (US)
Kieran Miller of Palo Alto CA (US)
Sudharshan Sugavanesh Udhayakumar of San Jose CA (US)
Compliant Pad Spacer for Three-Dimensional Integrated Circuit Package - A simplified explanation of the abstract
This abstract first appeared for US patent application 17885022 titled 'Compliant Pad Spacer for Three-Dimensional Integrated Circuit Package
Simplified Explanation
The compliant pad spacer in a three-dimensional IC packaging provides support among substrates to minimize warpage and collapse effects.
- Utilizes insulating material with ceramic fillers
- Supports packing substrates, interposers, or PCBs
- Minimizes substrate warpage and structural collapse
Potential Applications
- Three-dimensional IC packaging
- Electronic devices
- Semiconductor industry
Problems Solved
- Substrate warpage
- Structural collapse in IC packaging
Benefits
- Improved support among substrates
- Minimized effects of warpage and collapse
- Enhanced reliability of IC packaging
Original Abstract Submitted
A compliant pad spacer utilized in a three-dimensional IC packaging is provided. The compliant pad spacer may be utilized to provide adequate support among the substrates or boards, such as packing substrates, interposers or print circuit broads (PCBs), so as to minimize the effects of substrate warpage or structural collapse in the IC packaging. In one example, the compliant pad spacer includes an insulating material, such as silicon-based polymer composites having ceramic fillers disposed therein.
