17881747. SEMICONDUCTOR MEMORY DEVICE OF 2T-1C STRUCTURE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR MEMORY DEVICE OF 2T-1C STRUCTURE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Jongman Park of Hwaseong-si (KR)
SEMICONDUCTOR MEMORY DEVICE OF 2T-1C STRUCTURE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17881747 titled 'SEMICONDUCTOR MEMORY DEVICE OF 2T-1C STRUCTURE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The patent application describes a semiconductor memory device that includes first and second bit lines, an interlayer insulating layer, a groove, a first channel pattern, a second channel pattern, a word line, first and second electrodes, and a dielectric layer.
- The first and second bit lines are spaced apart from each other.
- The interlayer insulating layer covers the first and second bit lines and includes a groove that extends to cross both of the bit lines.
- The first channel pattern is connected to the first bit line and is in contact with an inner side surface of the groove, covering the top surface of the interlayer insulating layer.
- The second channel pattern is connected to the second bit line and is in contact with the opposite inner side surface of the groove, also covering the top surface of the interlayer insulating layer.
- A word line is located in the groove.
- The first and second electrodes are on the interlayer insulating layer and are in contact with the first and second channel patterns, respectively.
- A dielectric layer is present between the first and second electrodes.
Potential Applications
- This technology can be used in various semiconductor memory devices, such as flash memory or DRAM.
- It can be applied in electronic devices like smartphones, tablets, and computers.
Problems Solved
- The described memory device solves the problem of efficiently storing and retrieving data in a compact and reliable manner.
- It addresses the challenge of reducing the size and increasing the capacity of semiconductor memory devices.
Benefits
- The use of the groove and channel patterns allows for a more compact design of the memory device.
- The presence of the dielectric layer enhances the performance and reliability of the device.
- The technology enables higher memory capacity and faster data access speeds.
Original Abstract Submitted
A semiconductor memory device may include first and second bit lines spaced apart from each other, an interlayer insulating layer covering the first and second bit lines and including a groove extending to cross both of the first and second bit lines, a first channel pattern connected to the first bit line and in contact with an inner side surface of the groove and covering a top surface of the interlayer insulating layer, a second channel pattern connected to the second bit line and in contact with an opposite inner side surface of the groove and covering the top surface of the interlayer insulating layer, a word line in the groove, first and second electrodes on the interlayer insulating layer and in contact with the first and second channel patterns, respectively, and a dielectric layer between the first and second electrodes.
