17881187. MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Jungmyung Kang of Hwaseong-si (KR)
Sangyeop Baeck of Yongin-si (KR)
Dongwook Seo of Hwaseong-si (KR)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17881187 titled 'MEMORY DEVICE
Simplified Explanation
The patent application describes a memory device that includes a bit cell array, a write driver, and a write auxiliary circuit.
- The memory device has a bit cell array with multiple bit cells connected to a first auxiliary line.
- During a write operation, the write driver applies a bit line voltage to a bit line in the bit cell array.
- The write auxiliary circuit is connected to the first auxiliary line and a second auxiliary line, and it lowers the cell power voltage for a specific bit cell during the write operation.
- The cell power voltage is supplied to the first auxiliary line through the second auxiliary line, and it is sequentially supplied from the first bit cell to a second bit cell adjacent to the write driver through the first auxiliary line.
Potential applications of this technology:
- Memory devices in computers, smartphones, and other electronic devices.
- Data storage systems in cloud computing and data centers.
- Embedded memory in automotive electronics and IoT devices.
Problems solved by this technology:
- Reduces power consumption during write operations by lowering the cell power voltage for specific bit cells.
- Prevents overloading of bit cells that are spaced apart from the write driver.
Benefits of this technology:
- Improved energy efficiency in memory devices.
- Enhanced reliability and lifespan of memory cells.
- Enables faster and more efficient write operations.
Original Abstract Submitted
A memory device includes a bit cell array including a plurality of bit cells connected to a first auxiliary line to which a cell power voltage is supplied; a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the bit cell array during a write operation; and a write auxiliary circuit connected to the first auxiliary line and a second auxiliary line extending in parallel to the first auxiliary line, and configured to lower a cell power voltage for a first bit cell spaced apart from the write driver during the write operation, wherein the cell power voltage is supplied to the first auxiliary line through the second auxiliary line, and in sequence from the first bit cell to a second bit cell adjacent to the write driver through the first auxiliary line.
