17879106. REDISTRIBUTION SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
REDISTRIBUTION SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Organization Name
Inventor(s)
HYEONJEONG Hwang of Cheonan-si (KR)
KYOUNG LIM Suk of Suwon-si (KR)
REDISTRIBUTION SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17879106 titled 'REDISTRIBUTION SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Simplified Explanation
The abstract describes a redistribution substrate for electronic devices. The substrate includes multiple layers with different patterns to facilitate interconnections between components.
- The first interconnection layer has a first insulating pattern, along with two dummy patterns (dot patterns and a plate pattern) within it.
- The second interconnection layer is stacked on top of the first layer and has a second insulating pattern, along with a signal pattern and a power/ground pattern within it.
- The first dummy pattern is positioned below the signal pattern, while the second dummy pattern is positioned below the power/ground pattern.
Potential applications of this technology:
- Electronic devices and systems that require efficient interconnections between components.
- Integrated circuits, microprocessors, and other electronic components that need redistribution substrates for signal and power/ground connections.
Problems solved by this technology:
- Provides a simplified and efficient method for interconnecting components in electronic devices.
- Helps to reduce signal interference and improve overall performance.
Benefits of this technology:
- Improved signal integrity and reduced noise interference.
- Enhanced performance and reliability of electronic devices.
- Simplified manufacturing process for redistribution substrates.
Original Abstract Submitted
A redistribution substrate may include a first interconnection layer having a first insulating pattern, a first dummy pattern and a second dummy pattern, the first and second dummy patterns being in the first insulating pattern, and a second interconnection layer stacked on the first interconnection layer, the second interconnection layer having a second insulating pattern, a signal pattern and a power/ground pattern, the signal and power/ground patterns being in the second insulating pattern. The first dummy pattern may be located below the signal pattern, and the second dummy pattern may be located below the power/ground pattern. The first dummy pattern may include dot patterns, and the second dummy pattern may include a plate pattern.
