17876847. PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Organization Name
Inventor(s)
PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17876847 titled 'PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Simplified Explanation
The abstract of the patent application describes a package substrate that includes several layers and structures. Here is a simplified explanation of the abstract:
- The package substrate consists of a dielectric layer, a conductive pad, and a wiring pattern on top of the dielectric layer.
- A protection layer is applied on the dielectric layer, covering the wiring pattern.
- Between the dielectric layer and the protection layer, there is an undercut region where the two surfaces face each other.
- The undercut region exposes a sidewall of the wiring pattern.
- The width of the undercut region is smaller than the width of the wiring pattern.
Potential applications of this technology:
- Integrated circuits and electronic devices that require a package substrate.
- Semiconductor packaging and assembly processes.
Problems solved by this technology:
- Protection of the wiring pattern from external factors such as moisture, dust, or physical damage.
- Ensuring proper electrical connectivity and signal transmission within the package substrate.
Benefits of this technology:
- Enhanced protection of the wiring pattern due to the presence of the protection layer and the undercut region.
- Improved reliability and durability of the package substrate.
- Efficient use of space, as the width of the undercut region is smaller than the wiring pattern.
Original Abstract Submitted
A package substrate includes a dielectric layer, a conductive pad and a wiring pattern on the dielectric layer, a protection layer on the dielectric layer, the protection layer covering the wiring pattern, and an undercut region between facing surfaces of the dielectric layer and the protection layer, the undercut region exposing a sidewall of the wiring pattern, and a width of the undercut region being less than a width of the wiring pattern.
