17876240. SEMICONDUCTOR PACKAGE STRUCTURE HAVING INTERPOSER SUBSTRATE, AND STACKED SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR PACKAGE STRUCTURE HAVING INTERPOSER SUBSTRATE, AND STACKED SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING THE SAME
Organization Name
Inventor(s)
SUNCHUL Kim of HWASEONG-SI (KR)
SEUNGHWAN Baek of CHEONAN-SI (KR)
SEMICONDUCTOR PACKAGE STRUCTURE HAVING INTERPOSER SUBSTRATE, AND STACKED SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17876240 titled 'SEMICONDUCTOR PACKAGE STRUCTURE HAVING INTERPOSER SUBSTRATE, AND STACKED SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING THE SAME
Simplified Explanation
The patent application describes a semiconductor package structure that includes a semiconductor chip, a package substrate, and an interposer substrate.
- The semiconductor chip is placed on the package substrate.
- A lower connection bump is present on the package substrate.
- The interposer substrate is placed on the lower connection bump and the upper surface of the semiconductor chip.
- An upper connection bump is present on the lower surface of the interposer substrate.
- A support structure is present on the lower surface of the interposer substrate, providing support between the package substrate and the interposer substrate.
- The support structure includes a metal core ball and a ball cover layer surrounding the metal core ball.
- The ball cover layer gradually decreases in thickness from the interposer substrate to the package substrate cross-section.
Potential applications of this technology:
- Semiconductor packaging in various electronic devices such as smartphones, tablets, and computers.
- Integrated circuits and microprocessors in electronic devices.
Problems solved by this technology:
- Provides support between the package substrate and the interposer substrate, reducing the risk of damage or failure.
- Ensures reliable electrical connections between the semiconductor chip and the package substrate.
Benefits of this technology:
- Improved reliability and durability of semiconductor packages.
- Enhanced electrical performance and signal integrity.
- Simplified manufacturing process for semiconductor packaging.
Original Abstract Submitted
A semiconductor package structure includes a semiconductor chip on a package substrate; a lower connection bump on the package substrate; and an interposer substrate on the lower connection bump on the package substrate and an upper surface of the semiconductor chip. The semiconductor package structure includes an upper connection bump on a lower surface of the interposer substrate; and a support structure on a lower surface of the interposer substrate, spaced apart from the upper connection bump to provide support between the package substrate and the interposer substrate. The upper connection bump and the lower connection bump constitute a connection bump structure, and the support structure includes a metal core ball and a ball cover layer surrounding the metal core ball, wherein the ball cover layer is formed to gradually decrease in thickness in a direction from the interposer substrate to the package substrate cross-section.
