17871078. CORE MAPPING BASED ON LATENCY IN A MULTIPLE CORE PROCESSOR simplified abstract (Dell Products L.P.)
Contents
CORE MAPPING BASED ON LATENCY IN A MULTIPLE CORE PROCESSOR
Organization Name
Inventor(s)
Michael Christensen of Round Rock TX (US)
Yuwei Cai of Pflugerville TX (US)
CORE MAPPING BASED ON LATENCY IN A MULTIPLE CORE PROCESSOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 17871078 titled 'CORE MAPPING BASED ON LATENCY IN A MULTIPLE CORE PROCESSOR
Simplified Explanation
The abstract describes an information handling system that includes a memory and a basic input/output system (BIOS). The BIOS is responsible for mapping multiple processor cores to multiple integrated memory controllers of a multiple core processor. It calculates a different latency for each processor core and assigns mapping priority levels based on these latencies. The BIOS then maps each processor core to an associated integrated memory controller and stores the map in memory.
- The BIOS receives a request to map multiple processor cores to multiple integrated memory controllers.
- It calculates a different latency for each processor core.
- Based on the calculated latencies, the BIOS assigns mapping priority levels to the processor cores.
- The BIOS maps each processor core to an associated integrated memory controller.
- The map of the processor cores is stored in memory.
Potential applications of this technology:
- High-performance computing systems that require efficient mapping of processor cores to memory controllers.
- Multi-core processors used in data centers or cloud computing environments.
Problems solved by this technology:
- Efficiently mapping processor cores to memory controllers to optimize performance.
- Avoiding bottlenecks and reducing latency in accessing memory.
Benefits of this technology:
- Improved performance and efficiency in information handling systems.
- Enhanced scalability and flexibility in multi-core processor architectures.
- Better utilization of resources and improved overall system performance.
Original Abstract Submitted
An information handling system includes a memory, and a basic input/output system (BIOS). The BIOS receives a request to map multiple processor cores to multiple integrated memory controllers of a multiple core processor. In response to the reception of the request, the BIOS calculates a different latency for each of the processor cores. Based on the calculated different latency for each of the processor cores, the BIOS assigns mapping priority levels to the processor cores of the multiple core processor. Based on the mapping priority levels, the BIOS maps each of the processor cores to an associated one of the integrated memory controllers. The BIOS stores the map of the processor cores in the memory.
