17870545. SEMICONDUCTOR DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Gyuseong Kang of Goyang-si (KR)
SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17870545 titled 'SEMICONDUCTOR DEVICE
Simplified Explanation
The patent application describes a semiconductor device that includes two memory cell arrays, an input/output circuit, and column decoders. The device also includes reference cells and dummy cells in both memory cell arrays.
- The first memory cell array has first memory cells, first reference cells, and first dummy cells.
- The second memory cell array has second memory cells, second reference cells, and second dummy cells.
- An input/output circuit is provided between the first and second memory cell arrays.
- A first column decoder is connected between the first memory cell array and the input/output circuit.
- A second column decoder is connected between the second memory cell array and the input/output circuit.
- The second column decoder connects one of the second dummy cells and the second memory cells to a selected sense amplifier of the input/output circuit when the first column decoder connects a selected first memory cell to the selected sense amplifier.
Potential applications of this technology:
- Memory devices in electronic devices such as smartphones, tablets, and computers.
- Data storage in cloud computing and data centers.
- High-speed data processing in artificial intelligence and machine learning applications.
Problems solved by this technology:
- Efficient utilization of memory cell arrays by using reference cells and dummy cells.
- Improved data transfer and processing speed by connecting selected memory cells to sense amplifiers.
Benefits of this technology:
- Increased memory capacity and performance.
- Reduced power consumption and improved energy efficiency.
- Enhanced reliability and data integrity.
Original Abstract Submitted
A semiconductor device includes a first memory cell array including a plurality of first memory cells, a plurality of first reference cells and a plurality of first dummy cells, a second memory cell array including a plurality of second memory cells, a plurality of second reference cells and a plurality of second dummy cells, an input/output circuit provided between the first memory cell array and the second memory cell array, a first column decoder connected between the first memory cell array and the input/output circuit and a second column decoder connected between the second memory cell array and the input/output circuit. The second column decoder connects one of the plurality of second dummy cells and the plurality of second memory cells to a selected sense amplifier of the input/output circuit, when the first column decoder connects a selected first memory cell to the selected sense amplifier.