17869061. MEMORY DEVICE, A MEMORY SYSTEM AND AN OPERATING METHOD OF THE MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE, A MEMORY SYSTEM AND AN OPERATING METHOD OF THE MEMORY DEVICE
Organization Name
Inventor(s)
MEMORY DEVICE, A MEMORY SYSTEM AND AN OPERATING METHOD OF THE MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17869061 titled 'MEMORY DEVICE, A MEMORY SYSTEM AND AN OPERATING METHOD OF THE MEMORY DEVICE
Simplified Explanation
The patent application describes a memory device that includes a memory bank with multiple memory cells and a memory interface circuit. The memory interface circuit is responsible for storing data in the memory cells based on command/address and data signals.
- The memory interface circuit has four pads to receive clock signals.
- The first buffer circuit samples the command/address signal when the first and third clock signals, which have opposite phases, are activated.
- The second buffer circuit samples the data signal when the first, second, third, and fourth clock signals are activated.
Potential applications of this technology:
- Memory devices in computers, smartphones, and other electronic devices.
- Storage devices in data centers and cloud computing systems.
- Embedded memory in automotive systems, IoT devices, and wearable technology.
Problems solved by this technology:
- Efficient storage of data in memory cells.
- Accurate sampling of command/address and data signals.
- Improved performance and reliability of memory devices.
Benefits of this technology:
- Faster data storage and retrieval.
- Enhanced memory interface circuit design.
- Increased memory device performance and efficiency.
Original Abstract Submitted
A memory device includes: a memory bank including a plurality of memory cells; and a memory interface circuit configured to store data in the plurality of memory cells based on a command/address signal and a data signal, wherein the memory interface circuit includes: first, second, third and fourth pads configured to receive first, second, third and fourth clock signals, respectively; a first buffer circuit configured to sample the command/address signal in response to an activation time of the first and third clock signals which have opposite phases from each other; and a second buffer circuit configured to sample the data signal in response to the activation time of the first clock signal, an activation time of the second clock signal, the activation time of the third clock signal and an activation time of the fourth clock signal.
