17868427. METHOD FOR CXL FALLBACK IN A CXL SYSTEM simplified abstract (Dell Products L.P.)
Contents
METHOD FOR CXL FALLBACK IN A CXL SYSTEM
Organization Name
Inventor(s)
Isaac Q. Wang of Austin TX (US)
Stuart Allen Berke of Austin TX (US)
METHOD FOR CXL FALLBACK IN A CXL SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 17868427 titled 'METHOD FOR CXL FALLBACK IN A CXL SYSTEM
Simplified Explanation
The abstract describes an information handling system that includes a processor and a Compute express link (CXL) device. The processor is connected to the CXL device through a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link and determines that the link failed to train to a first data rate. In response, the processor trains the link to a second data rate and operates the CXL device in a CXL mode.
- The patent/application involves an information handling system with a processor and a CXL device.
- The processor and CXL device are connected through a PCIe/CXL link.
- The processor initiates link training on the PCIe/CXL link.
- If the link fails to train to a first data rate, the processor trains it to a second data rate.
- The CXL device is then operated in a CXL mode in response to the successful training.
Potential Applications:
- High-performance computing systems
- Data centers
- Artificial intelligence and machine learning systems
Problems Solved:
- Ensures reliable and efficient communication between the processor and CXL device
- Addresses link training failures on the PCIe/CXL link
- Enables the use of CXL devices at different data rates
Benefits:
- Improved system performance and responsiveness
- Enhanced data transfer speeds between the processor and CXL device
- Flexibility in using CXL devices with varying data rates
Original Abstract Submitted
An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.
