17863697. MEMORY DEVICES simplified abstract (Samsung Electronics Co., Ltd.)
Contents
MEMORY DEVICES
Organization Name
Inventor(s)
Byungsoo Kim of Anyang-si (KR)
Sangwan Nam of Hwaseong-si (KR)
MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17863697 titled 'MEMORY DEVICES
Simplified Explanation
The memory device described in this patent application consists of two cell array regions separated by a separation region. Each region contains multiple memory blocks with stacked gate electrode layers.
- The gate electrode layers in the memory blocks include an upper select electrode layer with string select lines and a first electrode layer with first word lines.
- The first word lines have a first connection line that connects the first end portions of the lines on the opposite side of the separation region.
- Additionally, there are multiple second connection lines that connect some of the second end portions of the first word lines adjacent to the separation region.
- Each of the second connection lines is shorter than the first connection line.
Potential applications of this technology:
- Memory devices in electronic devices such as smartphones, tablets, and computers.
- Data storage in servers and data centers.
- Embedded memory in various electronic systems.
Problems solved by this technology:
- Efficient organization of memory blocks in a memory device.
- Improved connectivity between word lines in different regions of the memory device.
- Reduction in the length of connection lines, leading to improved performance and reduced power consumption.
Benefits of this technology:
- Higher memory density due to the stacked gate electrode layers.
- Enhanced data access speed and overall memory device performance.
- Lower power consumption, resulting in improved energy efficiency.
Original Abstract Submitted
A memory device includes a first cell array region and a second cell array region separated by a separation region, each including at least one memory block having a plurality of gate electrode layers stacked in a first direction. The gate electrode layers include an upper select electrode layer including a plurality of string select lines, and a first electrode layer including a plurality of first word lines arranged below the string select lines. The first word lines include a first connection line to connect first end portions of the first word lines positioned on the opposite side of the separation region to each other and a plurality of second connection lines to connect some of second end portions of the plurality of first word lines adjacent to the separation region to each other, wherein each of the second connection lines is shorter than the first connection line.
