17862496. THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND A METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND A METHOD OF FABRICATING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Jegwan Hwang of Suwon-si (KR)

Jihyung Kim of Seoul (KR)

Jeong Hoon Ahn of Seongnam-si (KR)

Jaehee Oh of Seongnam-si (KR)

Shaofeng Ding of Suwon-si (KR)

Won Ji Park of Suwon-si (KR)

WooSeong Jang of Suwon-si (KR)

Seokjun Hong of Suwon-si (KR)

THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND A METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17862496 titled 'THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND A METHOD OF FABRICATING THE SAME

Simplified Explanation

The abstract describes a three-dimensional integrated circuit structure that includes multiple layers and power delivery networks. It specifically focuses on the connection between the first and second power delivery networks through a bump and through electrode.

• The structure includes a first die with a power delivery network, substrate, device layer, and metal layer.
• A second die is placed on top of the first die, also with its own power delivery network, substrate, device layer, and metal layer.
• A through electrode extends from the first power delivery network to the top surface of the first metal layer.
• A bump is present on the through electrode, connecting it to the second power delivery network.
• The second power delivery network includes lower lines for power transfer to the second device layer, with a pad connected to the lowermost line.
• The first bump is positioned between the through electrode and the pad, establishing a connection between the first and second power delivery networks.

Potential applications of this technology:

• Three-dimensional integrated circuits can be used in various electronic devices, such as smartphones, computers, and IoT devices.
• This technology enables more efficient power delivery and connectivity within the integrated circuit structure.
• It allows for compact designs and improved performance in electronic devices.

Problems solved by this technology:

• Traditional two-dimensional integrated circuits have limitations in terms of power delivery and connectivity.
• This three-dimensional structure addresses these limitations by providing a more efficient and compact solution.
• It allows for better integration of multiple components and layers within the circuit.

Benefits of this technology:

• Improved power delivery efficiency and connectivity within the integrated circuit structure.
• Compact design, allowing for more components to be integrated into a smaller space.
• Enhanced performance and functionality of electronic devices.
• Potential for cost savings in manufacturing processes.

Original Abstract Submitted

A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.