17859870. SYSTEM ON CHIP FOR PERFORMING SCAN TEST AND METHOD OF DESIGNING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SYSTEM ON CHIP FOR PERFORMING SCAN TEST AND METHOD OF DESIGNING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

WOOHYUN Son of SUWON-SI (KR)

KISEOK Bae of HWASEONG-SI (KR)

SYSTEM ON CHIP FOR PERFORMING SCAN TEST AND METHOD OF DESIGNING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17859870 titled 'SYSTEM ON CHIP FOR PERFORMING SCAN TEST AND METHOD OF DESIGNING THE SAME

Simplified Explanation

The abstract describes a system on chip (SoC) that includes a one-time programmable (OTP) memory for storing secure data. It also includes an OTP controller with a shadow register for reading and storing the secure data. A power management unit receives an operation mode signal and outputs test mode information and a test valid signal. A test circuit receives the test mode information and test data from an external device and outputs a scan mode signal and a test mode signal based on the test data and a test deactivation signal.

  • The system on chip includes a one-time programmable (OTP) memory for storing secure data.
  • An OTP controller with a shadow register is used to read and store the secure data from the OTP memory.
  • A power management unit receives an operation mode signal from an external device and outputs test mode information and a test valid signal.
  • The test mode information indicates whether the operation mode is a test mode, and the test valid signal corresponds to the secure data.
  • A test circuit receives the test mode information and test data from the external device and outputs a scan mode signal and a test mode signal.
  • The scan mode signal and test mode signal are determined based on the test data and a test deactivation signal.
  • The test deactivation signal represents the chip development state in the secure data.

Potential applications of this technology:

  • Secure data storage and retrieval in systems on chips.
  • Test mode functionality for chip development and testing.

Problems solved by this technology:

  • Secure storage of sensitive data in a one-time programmable memory.
  • Efficient retrieval and storage of secure data using an OTP controller with a shadow register.
  • Accurate detection of test mode and test validity using a power management unit and test circuit.

Benefits of this technology:

  • Enhanced security for sensitive data stored in the OTP memory.
  • Improved efficiency and reliability in retrieving and storing secure data.
  • Accurate detection and control of test mode functionality during chip development and testing.


Original Abstract Submitted

A system on chip includes a one-time programmable (OTP) memory configured to store secure data, an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data, a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data, and a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and a test deactivation signal, wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.

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