17857015. BIT LINE SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)

BIT LINE SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Seongjin Cho of Hwaseong-si (KR)

BIT LINE SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17857015 titled 'BIT LINE SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME

Simplified Explanation

The abstract describes a bit line sense amplifier that is used in memory cells. The sense amplifier includes two inverters and two offset elements.

• The first inverter is connected to a complementary sensing bit line, while the second inverter is connected to a sensing bit line.
• The first offset element connects a bit line to the complementary sensing bit line, and the second offset element connects a complementary bit line to the sensing bit line.
• The offset cancellation signal controls the activation of the offset elements.
• During the first time interval, the offset elements are turned off and a capacitor of a memory cell is connected to the bit line.
• During the second time interval, the offset elements are turned on and the capacitor of the memory cell is disconnected from the bit line.

Potential applications of this technology:

• Memory cells in computer systems
• Storage devices such as solid-state drives (SSDs)
• Mobile devices like smartphones and tablets

Problems solved by this technology:

• Improves the accuracy and reliability of reading data from memory cells
• Reduces noise and interference in the sensing process

Benefits of this technology:

• Higher data integrity and accuracy
• Improved performance and efficiency of memory systems
• Enhanced reliability and durability of storage devices

Original Abstract Submitted

A bit line sense amplifier includes a first inverter having an output terminal connected to a complementary sensing bit line, a second inverter having an output terminal connected to a sensing bit line, a first offset element connecting a bit line to the complementary sensing bit line and a second offset element connecting a complementary bit line to the sensing bit line, in response to an offset cancellation signal. During a first time interval, the first offset element and the second offset element are turned off and a capacitor of a first memory cell is connected to the bit line. During a second time interval after the first time interval, the first offset element and the second offset element are turned on and the capacitor of the first memory cell is disconnected from the bit line.