17852593. MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND METHOD OF OPERATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)

MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND METHOD OF OPERATING THE SAME

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Hijung Kim of Suwon-si (KR)

Kwangchol Choe of Seoul (KR)

Kwangsook Noh of Suwon-si (KR)

Jaepil Lee of Seoul (KR)

MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND METHOD OF OPERATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17852593 titled 'MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND METHOD OF OPERATING THE SAME

Simplified Explanation

The abstract describes a memory device that includes a memory cell array and a clock buffer. The memory cell array has memory cells connected to wordlines and bitlines, and the clock buffer receives a clock signal for performing read or write operations on the memory cells. The clock buffer consists of multiple clock repeaters connected in series, with at least one pair of clock repeaters having different imbalanced driving capabilities.

• The memory device includes a memory cell array and a clock buffer.
• The memory cell array has memory cells connected to wordlines and bitlines.
• The clock buffer receives a clock signal for read or write operations on the memory cells.
• The clock buffer consists of multiple clock repeaters connected in series.
• At least one pair of clock repeaters in the buffer have different imbalanced driving capabilities.

Potential Applications

This technology can be applied in various memory devices, such as:

• Computer systems
• Mobile devices
• Embedded systems
• Data storage devices

Problems Solved

The technology addresses the following problems:

• Imbalanced driving capabilities in clock repeaters
• Efficient read and write operations on memory cells
• Clock signal synchronization in memory devices

Benefits

The technology offers the following benefits:

• Improved performance and reliability of memory devices
• Enhanced clock signal distribution
• Efficient utilization of clock repeaters
• Reduced power consumption

Original Abstract Submitted

A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.