17850488. SEMICONDUCTOR PACKAGE INCLUDING SUB-PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE INCLUDING SUB-PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

HYUNSOO Chung of HWASEONG-SI (KR)

DAEWOO Kim of SEONGNAM-SI (KR)

YOUNGLYONG Kim of ANYANG-SI (KR)

SEMICONDUCTOR PACKAGE INCLUDING SUB-PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17850488 titled 'SEMICONDUCTOR PACKAGE INCLUDING SUB-PACKAGE

Simplified Explanation

The semiconductor package described in the patent application includes several components and features:

  • The package consists of a redistribution wiring layer, a controller chip, a first sealant, through vias, and a sub-package.
  • The controller chip is centrally placed on the redistribution wiring layer and is buried in the first sealant.
  • The through vias connect the redistribution wiring layer to the controller chip through the first sealant.
  • The sub-package is located on the upper surface of the first sealant.
  • The sub-package includes two stack structures, each containing vertically stacked chips.
  • The first stack structure is positioned on one side of the controller chip, while the second stack structure is placed on the other side adjacent to the first stack structure in a horizontal direction.
  • The first and second stack structures are sealed by a second sealant.

Potential applications of this technology:

  • This semiconductor package design can be used in various electronic devices such as smartphones, tablets, laptops, and other portable devices.
  • It can also be applied in automotive electronics, industrial equipment, and communication devices.

Problems solved by this technology:

  • The design provides a compact and efficient way to integrate multiple chips into a single package, reducing the overall size and complexity of the electronic device.
  • The use of through vias and redistribution wiring layer allows for improved connectivity and signal transmission between the chips.
  • The sealing of the stack structures ensures protection against environmental factors such as moisture, dust, and physical damage.

Benefits of this technology:

  • The compact design saves space, making it suitable for miniaturized electronic devices.
  • The improved connectivity and signal transmission enhance the performance and reliability of the semiconductor package.
  • The sealing of the stack structures provides protection, increasing the durability and lifespan of the electronic device.


Original Abstract Submitted

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

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