17850475. CPP-AGNOSTIC SOURCE-DRAIN CONTACT FORMATION FOR GATE-ALL-AROUND DEVICES WITH DIELECTRIC ISOLATION simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

CPP-AGNOSTIC SOURCE-DRAIN CONTACT FORMATION FOR GATE-ALL-AROUND DEVICES WITH DIELECTRIC ISOLATION

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Julien Frougier of Albany NY (US)

Ruilong Xie of Niskayuna NY (US)

Kangguo Cheng of Schenectady NY (US)

CHANRO Park of CLIFTON PARK NY (US)

Oleg Gluschenkov of Tannersville NY (US)

CPP-AGNOSTIC SOURCE-DRAIN CONTACT FORMATION FOR GATE-ALL-AROUND DEVICES WITH DIELECTRIC ISOLATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17850475 titled 'CPP-AGNOSTIC SOURCE-DRAIN CONTACT FORMATION FOR GATE-ALL-AROUND DEVICES WITH DIELECTRIC ISOLATION

Simplified Explanation

The patent application describes a semiconductor structure that includes a source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region. It also includes at least one first semiconductor layer within the S/D region and at least one second semiconductor layer partially within a gate region. The second semiconductor layer extends into a spacer region to connect with the S/D epitaxial growth. The structure has different gate-to-gate spaces in different regions.

• The semiconductor structure includes S/D epitaxial growth over a dielectric isolation region.
• It has first and second semiconductor layers within the S/D and gate regions.
• The second semiconductor layer extends into a spacer region to connect with the S/D epitaxial growth.
• The structure has different gate-to-gate spaces in different regions.

Potential Applications

This technology can be applied in various semiconductor devices and integrated circuits, including but not limited to:

• Microprocessors
• Memory devices
• Power amplifiers
• Sensors

Problems Solved

The semiconductor structure addresses the following problems:

• Ensuring proper connection between the second semiconductor layer and the S/D epitaxial growth.
• Managing gate-to-gate spacing in different regions to optimize device performance.
• Providing a reliable and efficient structure for semiconductor devices.

Benefits

The benefits of this technology include:

• Improved connectivity between different semiconductor layers.
• Enhanced device performance through optimized gate-to-gate spacing.
• Reliable and efficient structure for semiconductor devices.
• Potential for improved functionality and integration in various applications.

Original Abstract Submitted

A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.