17849639. FORMING A FORKSHEET NANODEVICE simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)
Contents
FORMING A FORKSHEET NANODEVICE
Organization Name
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s)
Ruilong Xie of Niskayuna NY (US)
REINALDO Vega of Mahopac NY (US)
Julien Frougier of Albany NY (US)
Kangguo Cheng of Schenectady NY (US)
FORMING A FORKSHEET NANODEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17849639 titled 'FORMING A FORKSHEET NANODEVICE
Simplified Explanation
The patent application describes a semiconductor structure that includes a common substrate and two different types of complementary metal oxide semiconductor (CMOS) devices.
- The first CMOS device, called a forksheet device, is located on the common substrate and consists of an n-doped Field Effect Transistor (nFET) and a p-doped Field Effect Transistor (pFET). The effective width ratio (β) between the nFET and the pFET is defined.
- The second CMOS device, called a gate-all-around (GAA) nanosheet CMOS device, is adjacent to the forksheet device on the common substrate. It is a different type of CMOS device and has a different β value between its nFET and pFET.
- The second β value is at least 5 percent different from the first β value.
- The innovation lies in the combination of these two different CMOS devices with different β values on a common substrate.
Potential applications of this technology:
- This semiconductor structure can be used in various electronic devices, such as smartphones, tablets, computers, and other integrated circuits.
- It can improve the performance and efficiency of these electronic devices by utilizing the different characteristics of the two CMOS devices.
Problems solved by this technology:
- By combining different CMOS devices with different β values, the semiconductor structure can provide enhanced functionality and performance compared to traditional CMOS structures.
- It allows for better optimization of the semiconductor structure for specific applications and requirements.
Benefits of this technology:
- Improved performance and efficiency of electronic devices.
- Enhanced functionality and versatility of the semiconductor structure.
- Better optimization and customization for specific applications.
Original Abstract Submitted
A semiconductor structure includes a common substrate; a first forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate and that has an nFET (n-doped Field Effect Transistor) and a pFET (p-doped Field Effect Transistor) and has a first β (effective width ratio) between the nFET and the pFET; and a second forksheet device that is adjacent to the first forksheet device on the common substrate and that has a second β between a second nFET and a second pFET. The second β is different than the first β by at least 5 percent. Another semiconductor structure includes a common substrate; a forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate; and a gate-all-around (GAA) nanosheet CMOS device that is located on the common substrate and is adjacent to the forksheet device.
