17849100. ADJUSTING REFRESH RATE DURING SELF-REFRESH STATE simplified abstract (MICRON TECHNOLOGY, INC.)
Contents
ADJUSTING REFRESH RATE DURING SELF-REFRESH STATE
Organization Name
Inventor(s)
John E. Riley of McKinney TX (US)
Joo-Sang Lee of Frisco TX (US)
Scott E. Smith of Plano TX (US)
ADJUSTING REFRESH RATE DURING SELF-REFRESH STATE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17849100 titled 'ADJUSTING REFRESH RATE DURING SELF-REFRESH STATE
Simplified Explanation
The patent application describes methods, systems, and devices for adjusting the refresh rate of a memory system during a self-refresh state.
- The memory system enters a self-refresh state and performs a first set of refresh operations on a set of memory cells at a certain rate.
- The memory system determines if a counter associated with the refresh operations satisfies a threshold for a second time while in the self-refresh state.
- If the counter satisfies the threshold for the second time, a flip-flop circuit modifies its output.
- The memory system then decreases the rate of executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.
Potential applications of this technology:
- Memory systems in electronic devices such as smartphones, tablets, and computers.
- Embedded systems and microcontrollers that utilize memory for data storage.
Problems solved by this technology:
- Efficient management of memory refresh operations during a self-refresh state.
- Reducing power consumption by adjusting the refresh rate based on specific conditions.
Benefits of this technology:
- Improved power efficiency by dynamically adjusting the refresh rate.
- Enhanced performance and reliability of memory systems.
- Extended battery life for portable electronic devices.
Original Abstract Submitted
Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.
